Design Engineering Manager – Power Management

Job Description: Design Engineering Manager – Power Management (Gate Drivers, IPMs, & Silicon Capacitors) Location: Remote Role Overview We are seeking a highly skilled Lead IC Design Engineer to architect and design our next-generation Power Management ICs. In this role, you will serve as the primary technical authority for the development of high-performance Gate Drivers, Intelligent Power Modules (IPMs), and advanced Silicon Capacitor technologies. You will drive the hands-on execution of analog and mixed-signal designs, define block-level architectures, and provide technical mentorship to junior design and layout engineers to deliver market-leading power solutions. This high visibility role involves extensive interaction with management and cross-functional teams, such as Device Engineering, System Applications, and Packaging Key Responsibilities Technical Architecture: Define and architect high-voltage gate drivers, IPM protection circuits, and integrated silicon capacitor structures. Hands-On Design: Perform transistor-level design, simulation, and verification of complex analog and mixed-signal power blocks. Silicon Integration: Lead the integration of passive silicon capacitors into advanced multi-chip modules and system-in-package topologies. Technical Mentorship: Provide technical guidance, code reviews, and design verification oversight to junior and mid-level engineering staff. Tape-Out Ownership: Drive the execution of the IC development lifecycle from schematic capture and layout supervision through tape-out. Silicon Validation: Partner with product and test engineering to characterize, debug, and validate first-silicon in the lab. Required Qualifications Education: Master’s or Ph.D. in Electrical Engineering or a related technical field. Experience: Minimum of 7+ years of hands-on IC design experience, with a proven track record of successful production tape-outs. Power Expertise: Deep technical knowledge of high-voltage gate driver architectures, level shifters, and isolation techniques. Passive Modeling: Strong understanding of silicon capacitor fabrication processes, parasitic modeling, and high-frequency characterization. EDA Tools: Expert proficiency with Cadence Virtuoso, Spectre, Mentor Calibre, and mixed-signal simulation methodologies. Problem Solving: Exceptional laboratory debugging skills using oscilloscopes, spectrum analyzers, and high-voltage test equipment. Preferred Qualifications Experience with GaN and SiC power FET driving requirements. Knowledge of advanced multi-chip module (MCM) packaging and SiP (System-in-Package) design. We are an equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, national origin, disability status, protected veteran status, or any other characteristic protected by law. Originally posted on Himalayas